(1) Field of the Invention
The invention relates to integrated circuit manufacturing, and, more particularly, to a method to fabricate a metal silicide gate device in the manufacture of an integrated circuit device.
(2) Description of the Prior Art
Metal-oxide-semiconductor (MOS) devices are commonly used in the art of integrated circuits. MOS devices offer many advantages over, for example, bipolar devices, such as the ability to form millions of such devices on the surface of the integrated circuit and the very low gate current of these devices. In a typical, high density MOS product, the gate terminal is fabricated using polysilicon. This choice provides many benefits from a manufacturing and device standpoint. However, as device and feature sizes have continued to be reduced, the inherent disadvantages of polysilicon have received increased attention. When compared to a metal material, polysilicon has a relatively high resistivity. In a very small MOS device, or in a very high-speed application, the gate resistance, even of heavily doped polysilicon, can adversely limit the device performance. In addition, polysilicon inherently causes a depletion effect that must be compensated for using the threshold implant. This depletion effect further limits the application of polysilicon for the gate terminal material in very low supply voltage products.
The are several approaches in the art to improving the performance of the MOS transistor device by altering or replacing the polysilicon material. One approach is to replace the polysilicon layer with a metal layer as is shown in the process sequence illustrated in FIGS. 1 through 4. Referring specifically to FIG. 1, a partially completed integrated circuit device is shown in a cross sectional representation. The device comprises, at this point in the fabrication process, a semiconductor substrate 10 onto which are formed a series of temporary gates. Each gate is formed by a patterned polysilicon layer 18 overlying the substrate 10 with a dielectric layer 14 therebetween. Further processing has been performed to form source and drain regions 22. Spacers 26 have been formed as part of the lightly doped drain (LDD) and heavily doped source/drain system as is well-known in the art. A masking or capping layer 30 is formed overlying each polysilicon gate 18. An isolation layer 34 is formed overlying the substrate 10 and electrically isolating each gate.
At this stage in the process, the cross-section shows typical MOS devices with polysilicon gates 18. However, in this case, the gates 18 are temporary and serve to form the boundaries for permanent metal gates that will be formed by a damascene process. Referring now to FIG. 2, the capping layer 30, polysilicon layer 18, and dielectric layer 14 are completely removed to reveal gate openings 38. Referring now to FIG. 3, these openings are then filled by, first, forming a new dielectric layer 42 on the surface of the substrate 10 in the gate openings. Next, a metal layer 46, is deposited to fill the gate openings. Finally, referring now to FIG. 4, the metal layer 46 is polished down to remove the excess metal 46 between the gates and to thereby confine the metal layer 46 to the gate openings. The resulting metal gates 46 exhibit improved performance over the polysilicon gates, especially in dramatically reduced gate resistance. However, the process requires that the gate dielectric layer be re-formed and requires a polishing operation.
Several prior art inventions relate to silicide gate methods and devices. U.S. Pat. No. 6,465,309 B1 to Xiang et al describes a method to form a silicide gate transistor. An amorphous silicon layer is deposited following complete removal of a temporary polysilicon gate. U.S. Pat. No. 6,475,908 B1 to Lin et al describes a method to form metal silicide gate MOS transistors. In one embodiment, a temporary gate is formed and then removed. A metal/oxide gate is then formed in the opening. The metal is converted to silicide by ion implantation of silicon ions and thermal processing. U.S. Pat. No. 6,528,402 B2 to Tseng describes a method to form a self-aligned, silicide gate. A polysilicon gate is partially converted to metal silicide.